Memory controllers are used by computer systems to access memory subsystems, such as dynamic random access memory (DRAM) subsystems. FIG. 1 is a block diagram of a conventional DRAM subsystem 50, including one or more central processing units (CPUs) 52a and 52b, a memory controller 54 having input/output pins (I/Os), and a DRAM unit 56. The general operation of the DRAM subsystem 50 is well known, where the CPUs 52a and 52b instruct the memory controller 54 to write to and read from the DRAM unit 56. FIG. 2 is a block diagram of another conventional DRAM subsystem 60, including a CPU 62 and a DRAM unit 64. The DRAM subsystem 60 of FIG. 2 is similar to the DRAM subsystem 50 except that the CPU 62 of the DRAM subsystem 60 of FIG. 2 has an integrated memory controller. As such, the CPU 62 can communicate directly with the DRAM unit 64.
Typically, memory controllers are statically tuned at boot time to run the DRAM unit at the highest possible operating frequency that the memory controller and the DRAM unit will support. This enables the memory controller to perform at higher levels. A problem with some subsystems is that the memory controller is typically not re-tuned once it is tuned to a particular operating frequency. This becomes problematic, because in platforms with a wide workload dynamic range such as laptop computers, a DRAM subsystem, running at the highest possible frequency, consumes a large amount of power even when the computer system is operating in lower workload/power modes. In lower workload/power modes, special controls may be available to improve the power efficiency of a DRAM subsystem. Such special controls include power down, self-refresh, I/O tristating controls, and these special controls are used by many power-efficient platforms. However, the operating frequency of the DRAM unit is still not variable.
Accordingly, conventional solutions waste energy at several levels. First, dynamic power is typically higher because of the higher operating frequencies. Furthermore, maximum signal integrity requirements force the design to use the most aggressive features (e.g., increasing drive strength), which are power-hungry. Furthermore, at the highest operating frequencies, the clock interface between the CPU and the DRAM unit might be suboptimal due to putting the emphasis on bandwidth (e.g., by maximizing the operating frequency) instead of on latency (which can be more important for power efficiency). Conventional solutions have further shortcomings such as the use of a single set of timing parameters, which makes the lower-frequency modes suboptimal in terms of latency and causes the memory system to be less power-efficient.
Some memory controllers are designed to perform at a lower operating frequency when lower performance is less important. FIGS. 3 and 4 are timing diagrams showing read operations at 666 MHz and 333 MHz, respectively. Referring to both FIGS. 3 and 4 together, a problem with conventional solutions is that even though the operating frequency of a memory controller may be scaled down from its highest performance settings to lower performance settings (e.g., 666 MHz to 333 MHz), the number of cycles required to execute a given command (e.g., read command) remains the same (e.g., 10 cycles). So, the absolute amount of time to complete a cycle typically doubles (e.g., 1.5 nanoseconds per cycle to 3 nanoseconds per cycle). Consequently, the speed of the memory controller slows down substantially.
Accordingly, what is needed is an improved system and method for operating a memory controller. The present invention addresses such a need.